Corpus ID: 212441318

A Survey of Design Low Power Static Random Access Memory

  title={A Survey of Design Low Power Static Random Access Memory},
  author={L. Gupta},
  • L. Gupta
  • Published 2017
  • In this field research paper explores the design and analysis of Static Random Access memories (SRAMs) that focuses on optimizing delay and power. CMOS SRAM cell consumes very less power and have less read and write time. Higher cell ratios will decrease the read and write time and improve stability. PMOS semiconductor unit with fewer dimensions reduces the ability consumption. During this paper, 8T SRAM cell is implemented with reduced power and performance is good according read and write… CONTINUE READING
    1 Citations

    Figures from this paper

    • PDF


    Analysis of 8T SRAM Cell at Various Process Corners at 65 nm Process Technology
    • 16
    • PDF
    A low leakage and SNM free SRAM cell design in deep sub micron CMOS technology
    • S. Jain, Pankaj Agarwal
    • Materials Science, Computer Science
    • 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)
    • 2006
    • 50
    • PDF
    Ultra-low-power SRAM design in high variability advanced CMOS
    • N. Verma
    • Computer Science, Engineering
    • 2009
    • 11
    • PDF
    A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits
    • 134
    Stability and Static Noise Margin Analysis of Low-Power SRAM
    • R. Keerthi, C. Chen
    • Engineering
    • 2008 IEEE Instrumentation and Measurement Technology Conference
    • 2008
    • 34
    Leakage reduction in differential 10T SRAM cell using Gated VDD control technique
    • 8
    SNM Analysis of 6T SRAM at 32NM and 45NM Technique
    • 6
    Circuit techniques for ultra-low power subthreshold SRAMs
    • 27
    • PDF