A Survey and Taxonomy of GALS Design Styles

@article{Teehan2007ASA,
  title={A Survey and Taxonomy of GALS Design Styles},
  author={Paul Teehan and Mark R. Greenstreet and Guy Lemieux},
  journal={IEEE Design & Test of Computers},
  year={2007},
  volume={24}
}
Single-clocked digital systems are largely a thing of the past. Although most digital circuits remain synchronous, many designs feature multiple clock domains, often running at different frequencies. Using an asynchronous interconnect decouples the timing issues for the separate blocks. Systems employing such schemes are called globally asynchronous, locally synchronous (GALS). To minimize time to market, large SoC designs must integrate many functional blocks with minimal design effort. These… CONTINUE READING
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