A Survey and Evaluation of FPGA High-Level Synthesis Tools

@article{Nane2016ASA,
  title={A Survey and Evaluation of FPGA High-Level Synthesis Tools},
  author={R. Nane and V. Sima and C. Pilato and Jongsok Choi and B. Fort and Andrew Canis and Y. Chen and Hsuan Hsiao and S. Brown and Fabrizio Ferrandi and J. Anderson and K. Bertels},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year={2016},
  volume={35},
  pages={1591-1604}
}
  • R. Nane, V. Sima, +9 authors K. Bertels
  • Published 2016
  • Engineering, Computer Science
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level synthesis (HLS) is increasingly popular for the design of high-performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today's system complexity. HLS allows designers to work at a higher-level of abstraction by using a software program to specify the hardware functionality. Additionally, HLS is particularly interesting for designing field-programmable gate array circuits, where hardware implementations can be easily refined and replaced in the… Expand
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References

SHOWING 1-10 OF 103 REFERENCES
High-Level Synthesis for FPGAs: From Prototyping to Deployment
  • 617
  • PDF
An overview of today’s high-level synthesis tools
  • 143
  • PDF
C-based SoC design flow and EDA tools: an ASIC and system vendorperspective
  • 144
Harnessing the power of FPGAs using altera's OpenCL compiler
  • 20
  • PDF
Improving polyhedral code generation for high-level synthesis
  • 45
  • PDF
From software threads to parallel hardware in high-level synthesis for FPGAs
  • 74
  • PDF
The Garp Architecture and C Compiler
  • 449
  • PDF
System-level memory optimization for high-level synthesis of component-based SoCs
  • 16
  • PDF
SPARK: a high-level synthesis framework for applying parallelizing compiler transformations
  • 419
  • PDF
...
1
2
3
4
5
...