A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture

@article{Miyakoshi2006ASH,
  title={A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture},
  author={Junichi Miyakoshi and Yuichiro Murachi and Tetsuro Matsuno and Masaki Hamamoto and Takahiro Iinuma and Tomokazu Ishihara and Hiroshi Kawaguchi and Masayuki Miyama and Masahiko Yoshimoto},
  journal={IEICE Trans. Fundam. Electron. Commun. Comput. Sci.},
  year={2006},
  volume={89-A},
  pages={3623-3633}
}
We propose a sub-mW H.264 baseline-profile motion estimation processor for portable video applications. It features a VLSI-oriented block partitioning strategy and low-power SIMD/systolic-array datapath architecture, where the datapath can be switched between an SIMD and systolic array depending on processing flow. The processor supports all the seven kinds of block modes, and can handle three reference frames for a CIF (352 × 288) 30-fps to QCIF (176 × 144) 15-fps sequences with a quarter… 

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