A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing

@article{Luo2010ASV,
  title={A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing},
  author={Shien-Chun Luo and Lih-Yih Chiou},
  journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
  year={2010},
  volume={57},
  pages={440-445}
}
The access timing control of low-voltage static random access memory cells encounters crucial challenges in the presence of within-die (WID) variations, which induce severe delay mismatches between the timing-reference circuit and the bitlines. Prevention of early activation of sense amplifiers (SAs) is thus required to improve the yield. This brief proposes a novel SA-activation scheme by sensing differential bitlines locally and concurrently. The proposed structure effectively tolerates the… CONTINUE READING
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32 kb 10 T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS

  • I.-J. Chang, J.-J. Kim, S. P. Park, K. Roy
  • IEEE J. Solid State Circuits, vol. 44, no. 2, pp…
  • 2009
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