A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications

@article{atli2013ASF,
  title={A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications},
  author={Burak Çatli and Ali Nazemi and Tamer A. Ali and Siavash Fallahi and Yang Liu and Jaehyup Kim and Mohammed M. Abdul-Latif and Mahmoud Reza Ahmadi and Hassan Maarefi and Afshin Momtaz and Namik Kocaman},
  journal={Proceedings of the IEEE 2013 Custom Integrated Circuits Conference},
  year={2013},
  pages={1-4}
}
An 8.0 GHz to 12.2 GHz PLL with a capacitor multiplier-based active loop filter is designed in a 28 nm digital CMOS process. A passive loop filter-based version of the PLL is also implemented for comparison. While the PLL area is comparable to that of digital PLLs, the PLL performance is as good as that of an analog PLL that employs a passive loop filter. The capacitor multiplier-based active loop filter PLL has a jitter performance of 198 fs (rms), while its passive loop filter-based… CONTINUE READING
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