A Study on Multiplier Architecture Optimized for 32-bit Processor with 3-Stage Pipeline

@inproceedings{Jeong2004ASO,
  title={A Study on Multiplier Architecture Optimized for 32-bit Processor with 3-Stage Pipeline},
  author={Geun Young Jeong},
  year={2004}
}
  • Geun Young Jeong
  • Published 2004
This paper describes multiplier architectures optimized for 32 bit RISC processor with 3-stage pipeline. The multiplier of ARM7, the target processor, is variably carried out on the execution stage of pipeline within 7 cycles. The included multiplier employs a modified Booth's algorithm to produce 64 bit multiplication and addition product. We analyzed several multiplication algorithms such as radix-4 32×8, radix-4 32×16 and radix-8 32×32 to decide which multiplication architecture is most fit… CONTINUE READING