A Stacked Mesh 3D NoC Architecture Enabling Congestion-Aware and Reliable Inter-layer Communication

@article{Rahmani2011ASM,
  title={A Stacked Mesh 3D NoC Architecture Enabling Congestion-Aware and Reliable Inter-layer Communication},
  author={Amir-Mohammad Rahmani and Khalid Latif and Pasi Liljeberg and Juha Plosila and Hannu Tenhunen},
  journal={2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing},
  year={2011},
  pages={423-430}
}
In this paper, an efficient architecture to optimize system performance, power consumption, and reliability of stacked mesh 3D NoC is proposed. Stacked mesh is a feasible architecture which takes advantage of the short inter-layer wiring delays, while suffering from inefficient intermediate buffers. To cope with this, an inter-layer communication mechanism is developed to enhance the buffer utilization, load balancing, and system fault-tolerance. The mechanism benefits from a congestion-aware… CONTINUE READING

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References

Publications referenced by this paper.
SHOWING 1-10 OF 23 REFERENCES

Three-dimensional integrated circuits

VIEW 8 EXCERPTS
HIGHLY INFLUENTIAL

NED: A Novel Synthetic Traffic Pattern for Power/Performance Analysis of Network-on-chips Using Negative Exponential Distribution,

  • A. -M. Rahmani
  • Journal of Low Power Electronics,
  • 2009
VIEW 4 EXCERPTS
HIGHLY INFLUENTIAL

Design and Management of 3D Chip Multiprocessors Using Network-in-Memory,

  • F. Li
  • in Proc. of International Symposium on Computer Architecture,
  • 2006
VIEW 3 EXCERPTS
HIGHLY INFLUENTIAL

An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels,

  • A. -M. Rahmani
  • in Proc. of IEEE Computer Society Annual Symposium on VLSI,
  • 2010
VIEW 1 EXCERPT

TSV redundancy: Architecture and design issues in 3D IC

VIEW 1 EXCERPT

A Layer-Multiplexed 3D On-Chip Network Architecture

VIEW 2 EXCERPTS

Networks-on-chip in emerging interconnect paradigms: Advantages and challenges

VIEW 1 EXCERPT

MIRA: A Multi-layered On-Chip Interconnect Router Architecture

VIEW 1 EXCERPT