A Split-Load Interpolation-Amplifier-Array 300MS/s 8b Subranging ADC in 90nm CMOS

@article{Shimizu2008ASI,
  title={A Split-Load Interpolation-Amplifier-Array 300MS/s 8b Subranging ADC in 90nm CMOS},
  author={Yasuhide Shimizu and Shigemitsu Murayama and Kohei Kudoh and Hiroaki Yatsuda},
  journal={2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers},
  year={2008},
  pages={552-635}
}
The ADC is fabricated in 90 nm digital CMOS process. The chip consumes 34 mW at 300MS/s (f<sub>in</sub>=f<sub>s</sub>/2) from 1.2 V analog/digital and 2.5 V T/H-switches supply. At 100 MS/s (f<sub>in</sub>= f<sub>s</sub>/2), it consumes 6.7 mW from 0.75 V analog/digital and 1.5 V T/H-switches supplies. FOMs are 780 fJ/conversion-step at 300 MS/s (f<sub>in</sub>=f<sub>s</sub>/2), 680fJ/conversion-step at 300MS/s (f<sub>in</sub>=2MHz), 350 fJ/conversion- step at 100 MS/s (f<sub>in</sub>=f<sub>s… CONTINUE READING
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A 10-b 20-MHz 30-mW Pipelined Interpolating CMOS ADC

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  • IEEE J. Solid-State Circuits, vol. 28, no. 12, pp…
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