A Slew Rate Variation Compensated $2\times$ VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method

@article{Lee2019ASR,
  title={A Slew Rate Variation Compensated  \$2\times\$ VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method},
  author={Tzung-Je Lee and Tsung-Yi Tsai and Wei Chih Lin and U. Fat Chio and Chua-Chin Wang},
  journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
  year={2019},
  volume={66},
  pages={116-120}
}
A <inline-formula> <tex-math notation="LaTeX">$2{\boldsymbol \times }$ </tex-math></inline-formula>VDD I/O buffer based on deterministic PVT variation detection algorithms to achieve slew rate compensation is proposed in this brief. By using the P-PVT and N-PVT Variation Detectors consisting of an inverter and a capacitor, the slew rate variation is significantly reduced against the PVT variation. Besides, the source-drain leakage current is reduced by turning off the auxiliary current paths… CONTINUE READING

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Key Quantitative Results

  • Besides, the source-drain leakage current of the large driving MOS transistor is reduced by 50.9% without affecting the SR performance.

References

Publications referenced by this paper.
SHOWING 1-9 OF 9 REFERENCES

Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit

  • Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.
  • 2003

3.3V-5V compatible I/O circuit without thick gate oxide

  • 1992 Proceedings of the IEEE Custom Integrated Circuits Conference
  • 1992