A Simulink-to-FPGA implementation tool for enhanced design flow [educational applications]

@article{Shanblatt2005ASI,
  title={A Simulink-to-FPGA implementation tool for enhanced design flow [educational applications]},
  author={Michael A. Shanblatt and Brian Foulds},
  journal={2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)},
  year={2005},
  pages={89-90}
}
With the continued growth in complexity of FPGA-based designs, the need for a more flexible and efficient design methodology has arisen. Currently, most designs are accomplished through the use of HDL-centric flows. However, device densities have increased at a pace that such flows have become both cumbersome and outdated. The need for a more innovative and higher-level design flow that directly incorporates model simulation with hardware implementation is needed. Simulink is a well-known tool… CONTINUE READING
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References

Publications referenced by this paper.
Showing 1-7 of 7 references

SF2VHD: A StateFlow to VHDL Translator

  • K. Camera
  • Masters Thesis, UC Berkeley,
  • 2001
1 Excerpt

Recent Developments in High-Level Synthesis

  • Y. Lin
  • ACM Transactions on Design Automation of…
  • 1997
2 Excerpts

High-Level Synthesis: Introduction to Chip and System Synthesis, Kluwer Academic Publicshers

  • D. Gajski, N. Dutt, A. Wu, S. Lin
  • Norwell MA,
  • 1992
2 Excerpts

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