A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories

@inproceedings{Huang2002ASF,
  title={A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories},
  author={Rei-Fu Huang and Jin-Fu Li and Jen-Chieh Yeh and Cheng-Wen Wu},
  booktitle={MTDT},
  year={2002}
}
We present a simulator for evaluating the redundancy analysis (RA) algorithms. The simulator can calculate the repair rate (the ratio of the number of repaired memories to the number of defective memories) of the given RA algorithm and the associated memory configuration and redundancy structure. With the tool, the user also can easily assess and plan the redundant (spare) elements, and subsequently develop the built-in redundancy analysis (BIRA) algorithms and circuits that are essential for… CONTINUE READING
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