• Corpus ID: 4597063

A Self-calibrating current-steering 12-bit DAC based on new 1-bit self-test scheme

@inproceedings{Radulov2004ASC,
  title={A Self-calibrating current-steering 12-bit DAC based on new 1-bit self-test scheme},
  author={Georgi I. Radulov and Patrick J. Quinn and Ja Hans Hegt and Ahm Arthur van Roermund},
  year={2004}
}
This paper presents a self-test self-correction scheme for segmented current steering (CS) DACs. Prior art is critically analyzed. The new scheme improves the DAC linearity by improving the accuracy of the thermometer current sources. The algorithm, which controls the scheme, is described in details. A 12-bit CS DAC, with 6-6 segmentation, is implemented using the new scheme and algorithm. The DAC core is designed with 10-bit intrinsic linearity and this is improved to 12-bit level via… 

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References

SHOWING 1-10 OF 13 REFERENCES

A self-trimming 14-b 100-MS/s CMOS DAC

A 14-b 100-MS/s CMOS digital-analog converter (DAC) designed for high static and dynamic linearity is presented. The DAC is based on a central core of 15 thermometer decoded MSBs, 31 thermometer

A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC

A low-voltage low-power small-area and high-resolution digital-to-analog converter (DAC) for mixed-signal applications is Introduced. A binary weighted current steering DAC is a power-efficient

A dual 3.4V bitstream continuous calibration CMOS D/A converter with 110 dB dynamic range

A new generation D/A converter is presented, combining a true 18-bit dynamic range with easy application. This is achieved by introducing oversampling to 96 fs, digital filtering and noise-shaping.

Integrated analog-to-digital and digital-to-analog converters / Rudy Van De Plassche

This paper presents the converter as a black box, a guide to high-speed and high-resolution A/D and D/A converters, and some of the devices used in this converter, as well as some of their applications.

A 200MS/s 14b 97mW DAC in 0.18/spl mu/m CMOS

A fully analog loop calibrates 32 MSB floating current sources in the background to achieve 14b accuracy. Operating at 200MS/s, the 97mW DAC achieves maximum SFDR of 85dB in NRZ mode, 76dB in RZ

A 16b 400MS/s DAC with <-80dBc IMD to 300MHz and <-160dBm/Hz noise power spectral density

A current-output DAC with on-board calibration engine guarantees 16b monotonicity and achieves better than -160dBm/Hz noise power spectral density. Well bootstrapping, local bias generation and

Matching properties of MOS transistors

The matching properties of the threshold voltage, substrate factor and current factor of MOS transistors have been analysed and measured. Improvements of the existing theory are given, as well as

Probability, Random Variables and Stochastic Processes

This chapter discusses the concept of a Random Variable, the meaning of Probability, and the axioms of probability in terms of Markov Chains and Queueing Theory.

A 200MS/s 14b 97mW DAC in 0.18μm CMOS

  • IEEE International Solid-State Circuits Conference,
  • 2004

Onge, “A 16b 400MS/s DAC with <- 80dBc IMD to 300MHz and <- 160dBm/Hz Noise Power Spectral Densisty

  • 2003