A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator

This paper presents a 2.5D integrated microprocessor die, memory die, and accelerator die with 2.5D silicon interposer I/Os. The use of such 2.5D silicon interposer I/Os provide a scalable interconnection for core-core (up to 32 cores), core-memory (<inline-formula> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula> storage capacity) and… CONTINUE READING