A Scalable Front-End Architecture for Fast Instruction Delivery

  title={A Scalable Front-End Architecture for Fast Instruction Delivery},
  author={Glenn Reinman and Todd M. Austin and Brad Calder},
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet future processor execution targets requires that the performance of the instruction delivery mechanism scale with the execution core. Attaining these targets is a challenging task due to I-cache misses, branch mispredictions, and taken branches in the instruction stream. To further complicate matters, a VLSI interconnect… CONTINUE READING
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