A Scalable Front-End Architecture for Fast Instruction Delivery

@inproceedings{Reinman1999ASF,
  title={A Scalable Front-End Architecture for Fast Instruction Delivery},
  author={Glenn Reinman and Todd M. Austin and Brad Calder},
  booktitle={ISCA},
  year={1999}
}
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet future processor execution targets requires that the performance of the instruction delivery mechanism scale with the execution core. Attaining these targets is a challenging task due to I-cache misses, branch mispredictions, and taken branches in the instruction stream. To further complicate matters, a VLSI interconnect… CONTINUE READING
Highly Influential
This paper has highly influenced 17 other papers. REVIEW HIGHLY INFLUENTIAL CITATIONS
Highly Cited
This paper has 122 citations. REVIEW CITATIONS

Citations

Publications citing this paper.
Showing 1-10 of 77 extracted citations

122 Citations

01020'98'02'07'12'17
Citations per Year
Semantic Scholar estimates that this publication has 122 citations based on the available data.

See our FAQ for additional information.

References

Publications referenced by this paper.
Showing 1-5 of 5 references

Two-level adpative branch prediction and instruction fetch mechanisms for high performance superscalar processors

  • T. Yeh
  • Ph.D. Dissertation, University of Michigan,
  • 1993
Highly Influential
20 Excerpts

Scalable multi-level instruction fetch prediction

  • G. Reinman, B. Calder, T. Austin
  • Technical Report UCSD-CS99-613,
  • 1999
Highly Influential
3 Excerpts

Interconnect scaling - the real limiter to high-performance ulsi

  • M. Bohr
  • In Tech. Dig. of the International Electron…
  • 1995
Highly Influential
4 Excerpts

Similar Papers

Loading similar papers…