• Corpus ID: 212471371

A Review on Pipelined integer DCT architecture for HEVC

@inproceedings{Bendale2016ARO,
  title={A Review on Pipelined integer DCT architecture for HEVC},
  author={Mr. Rahul R. Bendale},
  year={2016}
}
Currently different types of transform techniques are used by different video codecs to achieve data compression during video frame transmission. Among them, Discrete cosine transform (DCT) is supported by most of modern video standards. The integer DCT is an approximation of DCT. It can be implemented exclusively with integer arithmetic. Integer DCT proves to be highly advantageous in cost and speed for hardware implementation. Implementation of an efficient discrete cosine transform with… 

References

SHOWING 1-9 OF 9 REFERENCES

Efficient hardware architecture for direct 2D DCT computation and its FPGA implementation

TLDR
A new architecture to achieve the computations of the 2D DCT directly without using any transposition memory is proposed and is suitable for usage with statistical rules to predict the zero quantized coefficients, which can considerably reduce the number of computation.

Efficient Hardware Architecture of a Modified 2-D Transform for the HEVC Standard

TLDR
An algorithm to compute the 4x4, 8x8 and 16x16 efficient two-dimensional transform for the HEVC standard providing less complexity and its hardware design and results showed frequency improvement reaching 96% when compared to an architecture described as the direct transcription of the algorithm.

Implementation of 2D-DCT Based on FPGA with Verilog HDL

TLDR
The row-column decomposition algorithm and pipelining are used to produce the high quality circuit design with the max clock frequency of 318MHz when implemented in a Xinlinx VIRTEX-II PRO FPGA chip.

Overview of the High Efficiency Video Coding (HEVC) Standard

TLDR
The main goal of the HEVC standardization effort is to enable significantly improved compression performance relative to existing standards-in the range of 50% bit-rate reduction for equal perceptual video quality.

Nouri Masmoudi3 -Efficient Hardware Architecture of a Modified 2-D Transform for the HEVC Standard‖ University of Sfax

  • Fatma Belghith*1, Hassen Loukil2

3Manoj Sharma1 -Trends in Video Compression Technologies and Detailed Performance Comparison of H.264/MPEG-AVC and H.265/MPEGHEVC‖, Bharati Vidyapeeth"s College of Engineering

  • International Journal of Engineering Research & Technology (IJERT)

Belkouch -Efficient hardware architecture for direct 2D DCT computation and its FPGA Implementation‖

  • 2013

2 Dr.S Ravi,3 V.Jayapradha 1SCSVMV University 2 Dr

  • MGR University