Corpus ID: 212449744

A Review on Clock Gating Methodologies for power minimization in VLSI circuits

@inproceedings{Singh2016ARO,
  title={A Review on Clock Gating Methodologies for power minimization in VLSI circuits},
  author={Harpreet Singh and Dr. Sukhwinder Singh},
  year={2016}
}
This research paper gives the introduction of the various clock gating techniques. It also provides the basic clock gating principles, benefits, limitations and enhancements in traditional clock gating scheme. Also it provides the details of parameters which can affect the implementation of the clock gating. As clock signal having great source of power consumption and this is a critical problem in every synchronous circuit. Clock gating is an effective way of reducing the dynamic power… Expand
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