A Reliable 3D MLC PCM Architecture with Resistance Drift Predictor


In this paper, we study the problem of resistance drift in an MLC Phase Change Memory (PCM) and propose a solution to circumvent its thermally-affected accelerated rate in 3D CMPs. Our scheme is based on the observation that instead of alleviating the problem of resistance drift by using large margins or error correction codes, the PCM read circuit can be reconfigured for tolerating most of the resistance drift errors in a dynamic manner. Through detailed characterization of memory access patterns for 22 applications, we propose an efficient mechanism to facilitate such reliable read scheme via tolerating (a) early-cycle resistance drifts by using narrow margins so that considerably saving energy of writes and improving cell endurance, and (b) late-cycle resistance drifts by accurately estimating resistance thresholds that separate states for sensing. Evaluations on a true 3D architecture, consisting of a 4-core CMP and a banked 2-bit PCM memory, show that our proposal provides 10<sup>6</sup> &#x00D7; lower error rate compared to the state-of-the-art designs of PCMs.

DOI: 10.1109/DSN.2014.31

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@article{Jalili2014AR3, title={A Reliable 3D MLC PCM Architecture with Resistance Drift Predictor}, author={Majid Jalili and Mohammad Arjomand and Hamid Sarbazi-Azad}, journal={2014 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks}, year={2014}, pages={204-215} }