A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC

@article{Noda2006ART,
  title={A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC},
  author={Hideyuki Noda and Katsumi Dosaka and Hans J{\"u}rgen Mattausch and Tetsushi Koide and Fukashi Morishita and Kazutami Arimoto},
  journal={IEICE Transactions},
  year={2006},
  volume={89-C},
  pages={1612-1619}
}
This paper describes a novel TCAM architecture designed for enhancing the soft-error immunity. An associated embedded DRAM and ECC circuits are placed next to TCAM macro to implement a unique methodology of recovering upset bits due to soft errors. The proposed configuration allows an improvement of soft-error immunity by 6 orders of magnitude compared with the conventional TCAM. We also propose a novel testing methodology of the soft-error rate with a fast parallel multi-bit test. In addition… CONTINUE READING

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