A Regular Layout for Parallel Adders

  title={A Regular Layout for Parallel Adders},
  author={Richard P. Brent and H. T. Kung},
  journal={IEEE Transactions on Computers},
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n. 

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