A Regular Layout for Parallel Adders

@article{Brent1982ARL,
  title={A Regular Layout for Parallel Adders},
  author={R. Brent and H. T. Kung},
  journal={IEEE Transactions on Computers},
  year={1982},
  volume={C-31},
  pages={260-264}
}
  • R. Brent, H. T. Kung
  • Published 1982
  • Computer Science
  • IEEE Transactions on Computers
  • With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n. 
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    References

    SHOWING 1-10 OF 19 REFERENCES
    The Area-Time Complexity of Binary Multiplication
    • 211
    • PDF
    The chip complexity of binary arithmetic
    • 118
    • PDF
    Area-Efficient VLSI Computation
    • 238
    • PDF
    On the Addition of Binary Numbers
    • R. Brent
    • Mathematics, Computer Science
    • IEEE Transactions on Computers
    • 1970
    • 53
    • Highly Influential
    Area-time complexity for VLSI
    • 381
    On the Time Required to Perform Addition
    • 127
    A Survey of Some Recent Contributions to Computer Arithmetic
    • H. L. Garner
    • Mathematics, Computer Science
    • IEEE Transactions on Computers
    • 1976
    • 22
    Computer Architecture: A Quantitative Approach
    • 11,297
    • PDF
    A regular layout for parallel adders
    • IEEE Transactions on Computers
    • 1982
    Introduction to VLSI
    • 1980