# A Regular Layout for Parallel Adders

@article{Brent1982ARL, title={A Regular Layout for Parallel Adders}, author={Richard P. Brent and H. T. Kung}, journal={IEEE Transactions on Computers}, year={1982}, volume={C-31}, pages={260-264} }

With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.

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## References

SHOWING 1-10 OF 17 REFERENCES

### The Area-Time Complexity of Binary Multiplication

- Computer ScienceJACM
- 1981

By using a model of computation which is a realistic approx~mauon to current and anucipated LSI or VLSI technology, it is shown that A T 2.0 is shown to be the time required to perform multtphcaUon of n-bit binary numbers on a chip.

### The chip complexity of binary arithmetic

- Computer ScienceSTOC '80
- 1980

Lower and upper bounds on the area-time complexity for chips that implement binary arithmetic are derived, assuming a model of computation which is intended to approximate, current and anticipated LSI or VLSI technology.

### On the Addition of Binary Numbers

- Computer ScienceIEEE Transactions on Computers
- 1970

An upper bound is derived for the time required to add numbers modulo 2n, using circuit elements with a limited fan-in and unit delay, and assuming that all numbers have the usual binary encoding.…

### Area-Time Complexity for VLSI

- Computer ScienceSTOC
- 1979

The complexity of the Discrete Fourier Transform (DFT) is studied with respect to a new model of computation appropr ia le to VLSI technology. This model focuses on two key parameters, the amount of…

### On the Time Required to Perform Addition

- Computer Science, MathematicsJACM
- 1965

If the group operation is adding integers modulo t~, it is shown that the lower bound behaves as log log a(t~), where a(,) is the largest power of a prime which divides ~.4bslracl.

### A Survey of Some Recent Contributions to Computer Arithmetic

- Computer ScienceIEEE Transactions on Computers
- 1976

This paper surveys some recent contributions to computer arithmetic. The survey includes floating-point arithmetic, nonstandard number systems, and the generation of elementary functions. The design…

### Computer Architecture: A Quantitative Approach

- Computer Science
- 1969

This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important…