A Register Allocation Technique Using Guarded PDG


Register allocation for instruction-level parallel processors involves problems that are not considered in register allocat,i on for scalar processors. First, when the same register is allocated to different variables, anti-dependence is gtmerated, which decreases instruction-level parallelism. Second, spill code should be inserted at a suitable position in… (More)
DOI: 10.1145/237578.237615

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