A Reduced Complexity Wallace Multiplier Reduction

  title={A Reduced Complexity Wallace Multiplier Reduction},
  author={Ron S. Waters and Earl E. Swartzlander},
  journal={IEEE Transactions on Computers},
Wallace high-speed multipliers use full adders and half adders in their reduction phase. Half adders do not reduce the number of partial product bits. Therefore, minimizing the number of half adders used in a multiplier reduction will reduce the complexity. A modification to the Wallace reduction is presented that ensures that the delay is the same as for the conventional Wallace reduction. The modified reduction method greatly reduces the number of half adders; producing implementations with… CONTINUE READING
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1 Excerpt

A Comparison of Dadda and Wallace Multiplier Delays

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1 Excerpt