A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure

@inproceedings{Haynes1998ARM,
  title={A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure},
  author={Simon D. Haynes and Peter Y. K. Cheung},
  booktitle={FCCM},
  year={1998}
}
Abstract  This paper presents a design for a reconfigurable multiplier array. The multiplier is constructed using an array of 4 bit Flexible Array Blocks (FABs), which could be embedded within a conventional FPGA structure. The array can be configured to perform a number of 4n x 4m bit signed/unsigned binary multiplications. We have estimated that the FABs are about 35 times more efficient in area than the equivalent multiplier implemented using a conventional FPGA structure alone. 

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