A Rank-Switching, Open-Row DRAM Controller for Time-Predictable Systems

@article{Krish2014ARO,
  title={A Rank-Switching, Open-Row DRAM Controller for Time-Predictable Systems},
  author={Yogen Krish and Zheng Pei Wu and Rodolfo Pellizzoni},
  journal={2014 26th Euromicro Conference on Real-Time Systems},
  year={2014},
  pages={27-38}
}
We introduce ROC, a Rank-switching, Open-row Controller for Double Data Rate Dynamic RAM (DDR DRAM). ROC is optimized for mixed-criticality multicore systems using modern DDR devices: compared to existing real-time memory controllers, it provides significantly lower worst case latency bounds for hard real-time tasks and supports throughput-oriented optimizations for soft real-time applications. The key to improved performance is an innovative rank-switching mechanism which hides the latency of… CONTINUE READING