A RISCy approach to VLSI

  title={A RISCy approach to VLSI},
  author={D. T. Fitzpatrick and John K. Foderaro and M. Katevenis and H. Landman and D. Patterson and J. B. Peek and Zvi Peshkess and C. S{\'e}quin and R. W. Sherburne and K. Van Dyke},
  journal={ACM Sigarch Computer Architecture News},
  • D. T. Fitzpatrick, John K. Foderaro, +7 authors K. Van Dyke
  • Published 1982
  • Computer Science
  • ACM Sigarch Computer Architecture News
  • A general trend in computers today is to increase the complexity of architectures along with the increasing potential of implementation technologies. The consequences of this complexity are increased design time, more design errors, inconsistent implementations, and the delay of single chip implementation (Patterson and Ditzel, 1980). The Reduced Instruction Set Computer (RISC) Project investigates a VLSI alternative to this trend. Our initial design is called RISC I. The judicious choice of a… CONTINUE READING
    35 Citations
    • 330
    • PDF
    Preliminary analysis of RISC architectures performance
    • 4
    Re-evaluation of the RISC I
    • 12
    Reduced instruction set computer architecture
    • 45
    • PDF
    The MODHEL microcomputer for RISCS study
    • 4
    Design methodology for full custom CMOS microcomputers
    • 12
    Measurements of a VLSI Design
    • 3
    • Highly Influenced