A QoS network architecture to interconnect large-scale VLSI neural networks

Abstract

This paper presents a network architecture to interconnect VLSI neural network chips to build a distributed ANN system. The architecture combines techniques from circuit switching and packet switching to provide two different service classes: isochronous connections and best-effort packet transfers. The isochronous connections are able to transport the axonal data of artificial neurons between VLSI ANN models that feature a speedup of multiples orders of magnitudes compared to biology. The connections use reserved bandwidth to provide loss-less transmissions as well as a low end-to-end delay with bounded jitter. Best-effort packet transfers use the remaining bandwidth for on-demand multi-purpose communication. The data forwarding is performed between synchronized instances of a dedicated switch architecture used at each network node. The switch is scalable in terms of port numbers and line speed. Its low complexity allows for an implementation within programmable logic or directly within a VLSI neural network chip. A reference implementation of the proposed network architecture is presented within an existing framework that hosts VLSI neural network chips operating at speedups of 10<sup>4</sup> to 10<sup>5</sup>. The network architecture is further not limited to VLSI neural networks, but it can in principle be used in all network environments that require isochronous connections as well as packet processing.

DOI: 10.1109/IJCNN.2009.5178983

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Cite this paper

@article{Philipp2009AQN, title={A QoS network architecture to interconnect large-scale VLSI neural networks}, author={Stefan Philipp and Johannes Schemmel and Karlheinz Meier}, journal={2009 International Joint Conference on Neural Networks}, year={2009}, pages={2525-2532} }