A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform

@article{Chen2001APP,
  title={A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform},
  author={Chien-Yu Chen and Zhong-Lan Yang and Tu-Chih Wang and Liang-Gee Chen},
  journal={Journal of VLSI signal processing systems for signal, image and video technology},
  year={2001},
  volume={28},
  pages={151-163}
}
  • Chien-Yu Chen, Zhong-Lan Yang, +1 author Liang-Gee Chen
  • Published 2001
  • Computer Science
  • Journal of VLSI signal processing systems for signal, image and video technology
  • Many VLSI architectures for computing the discrete wavelet transform (DWT) were presented, but the parallel input data sequence and the programmability of the 2-D DWT were rarely mentioned. In this paper, we present a parallel-processing VLSI architecture to compute the programmable 2-D DWT, including various wavelet filter lengths and various wavelet transform levels. The proposed architecture is very regular and easy for extension. To eliminate high frequency components, the pixel values… CONTINUE READING

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    Algorithms and architectures for 2D discrete wavelet transform

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    A hierarchical pipelining architecture and FPGA implementation for lifting-based 2-D DWT

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    An efficient VLSI implementation of the discrete wavelet transform using embedded instruction codes for symmetric filters

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    A Novel FPGA Implementation of a Wideband Sonar System for Target Motion Estimation

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