3D stacking of dies is an enabler for further miniaturization and increase of functionality. Individual dies are thinned down aggressively – down to approximately 20 um – and glued on top of each other. With such 3D ICs, the same power dissipation will lead to higher temperatures in a stacked-die package compared to a single-die package. Hence, there is a need to perform detailed thermal analysis in various phases of 3D IC design. Thermal analysis should be included in the design loop to assess the thermal consequences of design iterations and verify the final design before signoff. From a new methodology characterization point of view, for layouts consisting mainly of test structures, thermal analysis plays an important role in final chip verification. This article presents a practical approach to perform detailed thermal analysis of stacked-die packages, interconnections between the dies, and the complete electrical design layout. The methodology is demonstrated on a two stacked die structure in a BGA package.