• Corpus ID: 2459743

A Possible 100 MSPS Altera FPGA FFT Processor

@inproceedings{Hampson2002AP1,
  title={A Possible 100 MSPS Altera FPGA FFT Processor},
  author={Grant A. Hampson},
  year={2002}
}
This document describes a FPGA implementation and simulation of the FFT component of the IIP Radiometer RFI processor described in [1]. The FFT processor will ideally be capable of processing 100% of the input bandwidth (100 MSPS.) The chosen FFT length (1024) is a trade off of FFT bin width (approximately 100kHz) and possible RFI detection. This document describes a possible implementation in an Altera FPGA, as opposed to currently available ASIC designs [2, 3]. These ASICs are capable of… 

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