A Pipelined Memory Architecture for High Throughput Network Processors

  title={A Pipelined Memory Architecture for High Throughput Network Processors},
  author={Timothy Sherwood and George Varghese and Brad Calder},
Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. In this paper we focus on the design of a programmable architecture for backbone routers, based on the manipulation of wide irregular memory words, that can provide a feasible design alternative to custom ASICs. We propose a pipelined memory design that emphasizes worst-case throughput over latency, and co-explore architectural tradeoffs with the design of several important network… CONTINUE READING
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