Modeling and reduction of gate leakage during behavioral synthesis of nanoCMOS circuits
A new compact physics-based Alpha-Power Law MOSFET Model is introduced to enable projections of low power circuit performance for future generations of technology by linking the simple mathematical expressions of the original Alpha-Power Law Model with their physical origins. The new model, verified by HSPICE simulations and measured data, includes: 1) a subthreshold region of operation for evaluating the on/off current trade-off that becomes a dominant low power design issue as technology scales, 2) the effects of vertical and lateral high field mobility degradation and velocity saturation, and 3) threshold voltage roll-off. Model projections for MOSFET CV/I indicate a 2Xperformance opportunity compared to NTRS extrapolations for the 250, 180, and 150nm generations subject to maximum leakage current estimates of the roadmap. NTRS and model calculations converge at the 70nm technology generation, which exhibits pronounced on/off current interdependence for low power gigascale integration (GSI).