A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes

Abstract

In designing ASIPs (Application Specific Integrated Processors) the papers investigated so far have almost focused on the optimization of the CPU core and did not pay enough attention to the optimization of the RAM and ROM size together. This paper overcomes this limitation and proposes an optimization algorithm to define the best tradeoff between the CPU… (More)
DOI: 10.1109/ASPDAC.1998.669502

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Cite this paper

@inproceedings{Bnh1998APM, title={A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes}, author={Nguyen-Ngoc B{\`i}nh and Masaharu Imai and Yoshinori Takeuchi}, booktitle={ASP-DAC}, year={1998} }