A Partial Parallel folding Multiplier Design for 1024 bit Modular Multiplication


A 1056 times 32 bit partial parallel folding multiplier for security chip based on 0.25mum CMOS technology is proposed in this paper, of 200MHz working frequency. The multiplier is composed of two 572 times 32 bit partial parallel multipliers with reconfigurable data path between them, and this folding architecture can be divided in two for 544 times 544… (More)


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