A Parallel Structure for CMOS Four-Quadrant Analog Multipliers and Its Application to a 2-GHz RF Downconversion Mixer

@inproceedings{Hsiao1998APS,
  title={A Parallel Structure for CMOS Four-Quadrant Analog Multipliers and Its Application to a 2-GHz RF Downconversion Mixer},
  author={Shuo-Yuan Hsiao and Chung-Yu Wu},
  year={1998}
}
A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8m N-well doublepoly-double-metal CMOS technology. Experimental results have shown that, under a single 1.2-V supply voltage, the circuit has 0.89% linearity error… CONTINUE READING
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