A Parallel Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design

@article{Cong1993APB,
  title={A Parallel Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design},
  author={Jason Cong and M. Smith},
  journal={30th ACM/IEEE Design Automation Conference},
  year={1993},
  pages={755-760}
}
  • J. Cong, M. Smith
  • Published 1 July 1993
  • Computer Science
  • 30th ACM/IEEE Design Automation Conference
In this paper, we present a bottom-up clustering algorithm based on recursive collapsing of small cliques in a graph. The sizes of the small cliques are derived using random graph theory. This clustering algorithm leads to a natural parallel implementation in which multiple processors are used to identify clusters simultaneously. We also present a cluster-based partitioning method in which our clustering algorithm is used as a preprocessing step to both the bisection algorithm by Fiduccia and… 

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References

SHOWING 1-10 OF 37 REFERENCES
Finding clusters in VLSI circuits
TLDR
A fast heuristic algorithm based on a simple, local criterion is proposed that is able to prove that for highly structured circuits the clusters found by this algorithm correspond with high probability to the 'natural' clusters.
New spectral methods for ratio cut partitioning and clustering
  • L. Hagen, A. Kahng
  • Computer Science
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
  • 1992
TLDR
It is shown that the second smallest eigenvalue of a matrix derived from the netlist gives a provably good approximation of the optimal ratio cut partition cost.
A new approach to effective circuit clustering
TLDR
The DS quality measure, a general metric for evaluation of clustering algorithms, is established and motivates the RW-ST algorithm, a self-tuning clustering method based on random walks in the circuit netlist, which efficiently captures a globally good circuit clustering.
Fast spectral methods for ratio cut partitioning and clustering
  • L. Hagen, A. Kahng
  • Computer Science
    1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers
  • 1991
TLDR
The authors show a theoretical correspondence between the optimal ratio cut partition cost and the second smallest eigen value of a particular netlist-derived matrix, and present fast Lanczos-based methods for computing heuristic ratio cuts from the eigenvector of this second eigenvalue.
Towards efficient hierarchical designs by ratio cut partitioning
TLDR
It is demonstrated that the ratio cut algorithm can locate the clustering structures in the circuit and as much as 70% improvement over the Kernighan-Lin algorithm in terms of the proposed ratio metric.
Random walks for circuit clustering
  • J. Cong, L. Hagen, A. Kahng
  • Computer Science
    [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit
  • 1991
The authors introduce a fast, parallelizable approach to circuit clustering based on analysis of random walks in the netlist. The method yields good clustering solutions for classes of 'difficult'
Net partitions yield better module partitions
TLDR
The authors demonstrate that the dual intersection graph of the netlist strongly captures circuit properties relevant to partitioning, and highlights advantages to using the dual representation of the logic design, and confirms that net structure and interrelationships should constitute the primary descriptors of a circuit.
Improving the Performance of the Kernighan-Lin and Simulated Annealing Graph Bisection Algorithms
TLDR
An empirical study of a new heuristic, first proposed in [B87], that dramatically improves the performance of these bisection algorithms on graphs with small ( ≤ 4) average degree.
Maisie: A language and optimizing environment for distributed simulation
  • In Proc. of 1990 SCS Multiconference on Distributed Simulation,
  • 1990
A linear-time heuristic for improving network partitions
...
...