# A Parallel ASIC Architecture for Efficient Fractal Image Coding

@article{Acken1998APA, title={A Parallel ASIC Architecture for Efficient Fractal Image Coding}, author={Kevin P. Acken and Mary Jane Irwin and Robert Michael Owens}, journal={Journal of VLSI signal processing systems for signal, image and video technology}, year={1998}, volume={19}, pages={97-113} }

Fractal image coding is a compression technique with many promising features, but it has been primarily placed in the class of archival coding algorithms due to its computationally expensive encoding algorithm. Though fractal coding has been extensively optimized for speed, it is still not practical for real-time applications on most sequential machines. The problem with fractal coding lies in the large amount of pixel block comparisons that are required, which makes fractal coding betterâ€¦Â

## 12 Citations

Low-Delay Parallel Architecture for Fractal Image Compression

- Computer ScienceCircuits Syst. Signal Process.
- 2016

An efficient hardware architecture for implementing fractal image compression (FIC) algorithm aimed toward image compression with improved encoding speed and utilizes the benefits of isometric transformation without requiring additional cycles for every single matching operation.

VHDL design for hardware assistance of fractal image compression

- Computer ScienceIS&T/SPIE Electronic Imaging
- 2000

Simulations of the design suggest that an actual hardware implementation would be about one thousand times faster than a general purpose microprocessor based on similar IC technology, reducing the time required to optimally compress a 256 X 256 image using 8 X 8 range blocks from a few minutes to a fraction of a second.

High-speed implementation of fractal image compression in low cost FPGA

- Computer ScienceMicroprocess. Microsystems
- 2016

High-Speed Fractal Image Compression Featuring Deep Data Pipelining Strategy

- Computer ScienceIEEE Access
- 2018

Experimental results suggest that the proposed architecture is able to encode a $1024\times 1024$ size image in 10.8 ms with PSNR and CR averaging at 27 dB and 34:1, respectively, which is comparable to the state-of-the-art fractal processors.

Hardware Architecture of a Decoder for Fractal Image Compression

- Computer Science2019 Devices for Integrated Circuit (DevIC)
- 2019

This paper has proposed efficient hardware of a decoder for the fractal image compression and Controlled parallelism has been incorporated to speed up the decoding process.

Real-time implementation of Fractal Image Compression in low cost FPGA

- Computer Science2016 IEEE International Conference on Imaging Systems and Techniques (IST)
- 2016

A new parallel architecture is proposed for implementing a full-search FIC coding synthesized on a low-cost FPGA and optimized at circuit level in order to achieve a near real-time operation.

Hardware implementation of quadtree based fractal image decoder

- Computer Science2016 Twenty Second National Conference on Communication (NCC)
- 2016

This paper presents a simple hardware architecture for quadtree(QT) partitioning based fractal image decoder that spends less than 3 ms to decode a image of size 256 Ã— 256 with average image quality exceeding 33dB.

VLSI design of fast fractal image encoder

- Computer Science18th International Symposium on VLSI Design and Test
- 2014

A fast search based architecture for fractal image encoder, which efficiently exploits parallelism, is proposed, which can be considered as a successful approach for real time application for image compression.

Acceleration of Fractal Image Compression Using the Hardware-Software Co-design Methodology

- Computer Science2009 International Conference on Reconfigurable Computing and FPGAs
- 2009

A Hardware-Software Co-Design (HSC) of FIC which improves the compression time, obtaining an acceleration factor between 6.6 and 8.5.

Real time fractal image coder based on characteristic vector matching

- Computer ScienceImage Vis. Comput.
- 2010

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