A Novel Memory Subsystem Evaluation Framework for Chip Multiprocessors

  title={A Novel Memory Subsystem Evaluation Framework for Chip Multiprocessors},
  author={Fucen Zeng and Lin Qiao and Mingliang Liu and Zhizhong Tang},
  journal={2010 IEEE 12th International Conference on High Performance Computing and Communications (HPCC)},
This paper presents a fast and cycle-accurate memory subsystem modeling and evaluating framework for Chip Multiprocessors (CMPs), called TSIM (Tsinghua SIMulator), which gives a flexible and extensible approach to evaluating architecture designs, models or algorithms, including the network-on-chip interconnection, cache hardware prefetcher, memory system protocol, replacement policy, etc. TSIM is trace-driven, adopting a dynamic binary instrumentation technique to generate the running trace… CONTINUE READING