• Corpus ID: 43043339

A Novel Full Adder with High Speed Low Area

  title={A Novel Full Adder with High Speed Low Area},
  author={G. Shyam Kishore},
In most of the digital systems adder lies in the critical path that effects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is the main design aspect. The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has… 

Figures from this paper

Design and Analysis of Low Power High Performance 32-bit Ripple Carry Adder with Proposed Adder Cell

One-bit Full Adder based on human method with ten transistors is proposed and simulation for the designed circuits were also performed with 4-bit, 16-bit and 32-bit ripple carry adder.

A novel hybrid full adder using 13 transistors

A hybrid 1-bit full adder using complementary metal-oxide semiconductor (CMOS) logic style had been designed and design in both speed and energy consumption becomes even more significant as the word length of the adder increases.

Relative Performance Analysis of Different CMOS Full Adder Circuits

Eight different full adder circuits based on standard (std.) CMOS, CPL, 16Transistor, DCVSL, PTL, TGA, 14-Transistor and 8Transistor have been designed and implemented using Tanner EDA simulation tool to compare the propagation delay, power consumption and power delay product (PDP).

A 4-bit CMOS full adder of 1-bit hybrid 13T adder with a new SUM circuit

  • Shing Jie LeeS. H. Ruslan
  • Engineering, Computer Science
    2016 IEEE Student Conference on Research and Development (SCOReD)
  • 2016
In this paper, a 4-bit FA using complementary metal oxide semiconductor (CMOS) technology had been designed successfully and performance parameters such as power consumption and delay were compared to some of the existing designs.

Area, Delay And Power Comparison Of Adder Topologies

The pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area is presented and ripple carry adder is presented.

Comparison Between Various Types of Adder Topologies

The design of various adders are discussed and are compared on the basis of their performance parameters such as area, delay and power distribution.

Comparative Analysis of Low Power 10T and 14T Full Adder using Double Gate MOSFET at 45nm Technology

A comparative analysis of double gate 10T and double gate 14T adder at 45nm technology is described, which shows that 10T double gate full adder achieves 31.25% reduction in active power and 95% Reduction in leakage current as compared to 14T doubleGate Full adder.

Comparative analysis of 10T and 14T full adder at 45nm technology

A comparative analysis of 10T and 14T full adder is described with the aim of increasing power efficiency and reducing structure size at 45nm technology.

Comparative Analysis of 28 T Full Adder with 14 T Full Adder using 180 nm

A comparative analysis of 28T and 14T full adder is described with the aim of increasing power efficiency and reducing structure size at 180nm technology.


This work presents 20 different logical construction of 1-bit adder cell in CMOS logic and its performance is analyzed in terms of transistor count, delay and power dissipation, and the optimized equation is chosen to construct a full adder circuit in Terms of multiplexer.



Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates

This paper proposes a technique to build a total of 41 new 10-transistor full adders using novel XOR and XNOR gates in combination with existing ones to reduce the threshold-voltage loss of the pass transistors.

Design and analysis of 10-transistor full adders using novel XOR-XNOR gates

  • H. BuiA. Al-SheraidahYuke Wang
  • Engineering
    WCC 2000 - ICSP 2000. 2000 5th International Conference on Signal Processing Proceedings. 16th World Computer Congress 2000
  • 2000
A technique to build a total of 41 new 10-transistor full adders using novel XOR and XNOR gates in combination with existing ones is proposed, which consume less power in high frequencies, while three new adders consistently consume on average 10% less power and have higher speed.

The novel efficient design of XOR/XNOR function for adder applications

  • Kuo-Hsing ChengChih-Sheng Huang
  • Engineering
    ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357)
  • 1999
A new concept to implement high performance XOR/XNOR functions that using the pass transistor technique is proposed, which requires only six MOS transistors and shows that the proposed new circuit has the lowest power delay product performance.

Performance analysis of low-power 1-bit CMOS full adder cells

A performance analysis of 1-bit full-adder cell is presented, after the adder cell is anatomized into smaller modules, and several designs of each of them are developed, prototyped, simulated and analyzed.

Low-voltage low-power CMOS full adder

Low-power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products. In this regard many

A 14-transistor CMOS full adder with full voltage-swing nodes

  • M. Vesterbacka
  • Engineering
    1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)
  • 1999
It is explained how exclusive OR and NOR circuits (XOR/XNOR) are used to realize a general full adder circuit based on pass transistors, which is realized using only 14 MOSFETs, while having full voltage-swing in all circuit nodes.

Low-power logic styles: CMOS versus pass-transistor logic

This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.

New low-voltage circuits for XOR and XNOR

  • Hanho LeeG. Sobelman
  • Engineering
    Proceedings IEEE SOUTHEASTCON '97. 'Engineering the New Century'
  • 1997
The main design objectives for these new circuits are low power dissipation and full-voltage swing at a low supply voltage (V/sub dd/=2 V) and compared with previously known circuits and are shown to provide superior performance.

New efficient designs for XOR and XNOR functions on the transistor level

Two new methods are proposed to implement the exclusive-OR and exclusive-NOR functions on the transistor level. The first method uses non-complementary signal inputs and the least number of