• Corpus ID: 43043339

A Novel Full Adder with High Speed Low Area

@inproceedings{Kishore2011ANF,
  title={A Novel Full Adder with High Speed Low Area},
  author={G. Shyam Kishore},
  year={2011}
}
In most of the digital systems adder lies in the critical path that effects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is the main design aspect. The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has… 

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