A Novel Folding Technique for 3 Bit Flash ADC in Nanoscale

@article{Mishra2013ANF,
  title={A Novel Folding Technique for 3 Bit Flash ADC in Nanoscale},
  author={Saraswati Mishra and Abhay Vidyarthi and Sham Akashe},
  journal={2013 Third International Conference on Advanced Computing and Communication Technologies (ACCT)},
  year={2013},
  pages={307-311}
}
In this paper we design and optimized the low power and high speed 3 bit flash Analog-to-Digital Converter (ADC) using 45 nm technology. For high speed application Resolution, speed and power are optimized for implemented ADC. High integrated flash ADC is designed at three bit precision with operating voltage in range of 700 mV to 1V. This paper also describe the reduction in size of flash ADC and increase bit size of ADC using folding technique. Interpolation factor of 4 is introduced to… CONTINUE READING

References

Publications referenced by this paper.
SHOWING 1-10 OF 22 REFERENCES

A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC

  • IEEE Journal of Solid-State Circuits
  • 2009
VIEW 5 EXCERPTS
HIGHLY INFLUENTIAL

Micropower Data Converters: A Tutorial

  • IEEE Transactions on Circuits and Systems II: Express Briefs
  • 2010
VIEW 1 EXCERPT

A 1 . 8 V 1 . 6 GS / s 8 b selfcalibrating folding ADC with 7 . 26 ENOB at Nyquist frequency

C. Menkus, M. R. Tursi, O. Hidri, V. Pons
  • IEEE ISSCC Dig . Tech . Papers
  • 2008