A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box


In this paper, we present a novel Field Programmable Gate Array (FPGA) implementation of advanced encryption standard (AES128) algorithm based on the design of high performance S-Box built using reduced residue of prime numbers. The objective is to present an efficient hardware realization of AES-128 using very high speed integrated circuit hardware… (More)

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