This paper presents a low power and high speed ripple carry adder circuit design using a new CMOS domino logic family called feedthrough logic. Dynamic logic circuits are important as it provides better speed and has lesser transistor requirement when compared to static CMOS logic circuits. The proposed circuit has very low dynamic power consumption and lesser delay compared to the recently proposed circuit techniques for the dynamic logic styles. Problems associated with domino logic like limitation of non-inverting only logic, charge sharing and the need of output inverter are eliminated. The feedthrough logic (FTL) performs a partial evaluation in a computational block before its input signals reach a valid level, and performs a quick final evaluation as soon as the inputs arrive, leading to a reduction in the delay. The FTL is well suited to arithmetic circuits where the critical path consists of a large number of gates. A comparison has been done by simulating the proposed logic style based 10-bit ripple carry adder along with previous logic styles based RCAs. The results show that FTL is the simplest, fastest and consumes least power.