A Novel Dimension Reduction Technique for the CapacitanceExtraction of 3 D VLSI

  • InterconnectsWei Hongy, Weikai Sunz, Zhenhai Zhuy, Hao Jiy, Ben Songy, Wayne Wei-Ming Daizy
  • Published 2007

Abstract

In this paper, we present a new capacitance extraction method named Dimension Reduction Technique (DRT) for 3D VLSI interconnects. The DRT converts a complex 3D problem into a series of cascading simple 2D problems. Each 2D problem is solved separately, so we can choose the most eecient method according to the arrangement of conductors. More importantly, it… (More)

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