A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes

@article{Mansour2005AND,
  title={A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes},
  author={Mohammad M. Mansour and Naresh R. Shanbhag},
  journal={VLSI Signal Processing},
  year={2005},
  volume={40},
  pages={371-382}
}
A new parameterized-core-based design methodology targeted for programmable decoders for lowdensity parity-check (LDPC) codes is proposed. The methodology solves the two major drawbacks of excessive memory overhead and complex on-chip interconnect typical of existing decoder implementations which limit the scalability, degrade the error-correction capability, and restrict the domain of application of LDPC codes. Diverse memory and interconnect optimizations are performed at the code-design… CONTINUE READING
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