A Novel Clock Distribution System for CMOS VLSI

A novel alldigital clock distribm'on system for CMOS VLSI, capable of generating small-skew, four-phase, and non-overlap clock signals when supplied with only a onephase clock signal, is described. The frequency of the input clock signal can be decreased by 7% without a phaselocked loop (PU) by adopting this system. The key concept of this system is to… (More)