A Novel Architecture of Large Hybrid Cache With Reduced Energy

@article{He2017ANA,
  title={A Novel Architecture of Large Hybrid Cache With Reduced Energy},
  author={Jiacong He and Joseph Callenes-Sloan},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
  year={2017},
  volume={64},
  pages={3092-3102}
}
Energy becomes an inevitable challenge when using a large die-stacking dynamic random access memory (DRAM) cache. Although emerging spin-transfer-torque-RAM (STT-RAM) technology can efficiently reduce the static energy of large cache, it cannot completely replace DRAM cache due to the high write energy of STT-RAM. Recently, researchers have observed that there are many redundant bits written in the row buffer and futile bits written back to STT-RAM cells, which do not change the cells’ value… CONTINUE READING

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