A Nonlinearity Minimization-Oriented Resource-Saving Time-to-Digital Converter Implemented in a 28 nm Xilinx FPGA

@article{Wang2015ANM,
  title={A Nonlinearity Minimization-Oriented Resource-Saving Time-to-Digital Converter Implemented in a 28 nm Xilinx FPGA},
  author={Yonggang Wang and Chong Liu},
  journal={IEEE Transactions on Nuclear Science},
  year={2015},
  volume={62},
  pages={2003-2009}
}
Because large nonlinearity errors exist in the current tapped-delay line (TDL) style field programmable gate array (FPGA)-based time-to-digital converters (TDC), bin-by-bin calibration techniques have to be resorted for gaining a high measurement resolution. If the TDL in selected FPGAs is significantly affected by changes in ambient temperature, the bin-by-bin calibration table has to be updated as frequently as possible. The on-line calibration and calibration table updating increase the TDC… CONTINUE READING

References

Publications referenced by this paper.
SHOWING 1-10 OF 10 REFERENCES

A high-resolution ( ps RMS) 48-channel time-to-digital converter (TDC) implemented in a field programmable gate array (FPGA)

  • E. Bayer andM. Traxler
  • IEEE Trans. Nucl. Sci., vol. 58, no. 4, pp. 1547…
  • 2011
Highly Influential
4 Excerpts

Similar Papers

Loading similar papers…