A Non-Uniform Cache Architecture on Networks-on-Chip : A Fully Associative Approach with Pre-Promotion

@inproceedings{Kodama2004ANC,
  title={A Non-Uniform Cache Architecture on Networks-on-Chip : A Fully Associative Approach with Pre-Promotion},
  author={Akio Kodama and Toshinori Sato},
  year={2004}
}
Global interconnect becomes the delay bottleneck in microprocessor designs, and latency for large on-chip caches will be intolerable in deep submicron technologies. The recently-proposed Non-Uniform Cache Architectures (NUCAs) exploit the variation in access time across subarrays to reduce typical latency. In the dynamic NUCA (D-NUCA) design, a set-associative structure is selected and thus the flexibility of data placement and replacement is limited. This paper investigates one of the… CONTINUE READING

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