• DOI:10.47893/ijica.2011.1036
Corpus ID: 212510241

A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm

@inproceedings{Bala2011ANV,
  title={A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm},
  author={P. Bala and S. Raghavendra},
  year={2011}
}

P. Bala, S. Raghavendra

Published 2011

Mathematics

In a VLSI system, the pipeline architecture of high-speed modified Booth multipliers are used. The proposed multiplier circuits are based on the modified Booth algorithm. The pipeline technique which are the most widely used to accelerate the multiplication speed. To implement the optimally pipelined multipliers, many kinds of experiments have been conducted. The speed of the multipliers is greatly improved by properly deciding the number of pipeline stages and the positions for the pipeline… CONTINUE READING

View PDF

Save to Library

Create Alert

Cite

Launch Research Feed