A New Synthesis for Testability Scheme Using Two-Clock Control

Abstract

In the previous studies clock control has been inserted after design to improve the testability of a sequential circuit. In this paper we propose a two-clock control scheme that is included as a part of the logic synthesis of a nite state machine (fsm). The scheme has low area and delay overhead and it competes well with the scan method in its ability to initialize and observe circuit states. The states of the machine are assigned a pair of binary values using a novel split coding system. The purpose of the encoding is to ease navigation between any pair of states using a combination of normal and test-mode transitions. We require a Hamil-tonian cycle to exist in the state transition graph. Our investigation of the fsm benchmark shows that either such a cycle already exists or can be created with the insertion of a small number of transition edges. We also present synthesis results to validate the low area/time penalty claim.

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Cite this paper

@inproceedings{Mehta2007ANS, title={A New Synthesis for Testability Scheme Using Two-Clock Control}, author={Shashank K. Mehta and Kent L. Einspahrz and Sharad C. Seth and Kent L. Einspahr}, year={2007} }