Corpus ID: 8923878

A New Novel Low Power Floating Point Multiplier Implementation Using Vedic Multiplication Techniques

@inproceedings{Bai2013ANN,
  title={A New Novel Low Power Floating Point Multiplier Implementation Using Vedic Multiplication Techniques},
  author={Korra Tulasi Bai and J. Abhilash},
  year={2013}
}
In this paper, Vedic Multiplication Technique is used to implement IEEE 754 Floating point multiplier. The Urdhva-triyak bhyam sutra is used for the multiplication of Mantissa. The underflow and over flow cases are handled. The inputs to the multiplier are provided in IEEE 754, 32 bit format. The multiplier is implemented in VHDL and Virtex-5 FPGA is 
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A SINGLE/DOUBLE PRECISION FLOATING-POINT MULTIPLIER DESIGN FOR MULTIMEDIA APPLICATIONS
A parallel IEEE P754 decimal floating-point multiplier